View 23C8000-10_3109435.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

pin configuration 32 pdip features ? 1m x 8 organization single +5v power supply fast access time : 100/120/150/200ns totally static operation completely ttl compatible operating current : 25ma 1 p/n:pm0137 rev. 4.3, jul. 03, 2003 mx23c8000 8m-bit [1m x 8] cmos mask rom standby current : 15ua package - 32 pin plastic dip - 32 pin plastic sop - 32 pin plastic plcc - 32 pin plastic tsop general description the mx23c8000 is a 5v only, 8m-bit, read only memory. it is organized as 1m words by 8 bits, oper- ates from a single +5v supply, has a static standby mode, and has an access time of 100/120/150/200ns. it is designed to be compatible with all microprocessors and similar applications in which high performance, large bit storage and simple interfacing are important design con- siderations. mx23c8000 offers automatic power-down, with power- down controlled by the chip enable (ce) input. when ce goes high, the device automatically powers down and remains in a low-power standby modes as long as ce remains high. 32 sop 32 plcc 32 tsop 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 10 19 18 17 a19 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 vss vcc a18 a17 a14 a13 a8 a9 a11 oe a10 ce q7 q6 q5 q4 q3 mx23c8000 a11 a9 a8 a13 a14 a17 a18 vcc a19 a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe a10 ce q7 q6 q5 q4 q3 vss q2 q1 q0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 mx23c8000 mx23c8000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a19 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 vss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc a18 a17 a14 a13 a8 a9 a11 oe a10 ce q7 q6 q5 q4 q3 1 4 5 9 13 14 17 20 21 25 29 32 30 a14 a13 a8 a9 a11 oe a10 ce q7 a7 a6 a5 a4 a3 a2 a1 a0 dq q1 q2 vss q3 q4 q5 q6 a12 a15 a16 a19 vcc a18 a17 mx23c8000
2 p/n:pm0137 rev. 4.3, jul. 03, 2003 mx23c8000 pin description symbol pin function a0~a19 address inputs q0~q7 data outputs ce chip enable input oe output enable input vcc power supply pin (+5v) vss ground pin block diagram control logic output buffers q0~q7 ce oe a0~a19 address inputs y-decoder x-decoder y-select 8m bit rom array vcc vss . . . . . . . . . . . . . . . . absolute maximum ratings rating value ambient operating temperature 0 c to 70 c storage temperature -65 c to 125 c applied input voltage -0.5v to vcc+0.5 applied output voltage -0.5v to vcc+0.5 vcc to ground potential -0.5v to 7.0v power dissipation 1.0w note: minimum dc voltage on input or i/o pins is -0.5v. during voltage transitions, inputs may undershoot vss to - 2.0v for periods of up to 20ns. maximum dc voltage on input or i/o pins is vcc+0.5v. during voltage transitions, input may overshoot vcc to vcc+2.0v for periods of up to 20ns.
3 p/n:pm0137 rev. 4.3, jul. 03, 2003 mx23c8000 capacitance (ta = 25 c, f=1.0mhz (note 2)) item symbol min. max. unit conditions input capacitance cin - 10 pf vin=0v output capacitance cout - 10 pf vout=0v dc characteristics (ta = 0 c ~ 70 c, vcc = 5.0v 10%) item symbol min. max. conditions output high voltage voh 2.4v - ioh = -1.0ma output low voltage vol - 0.4v iol = 2.1ma input high voltage vih 2.2v vcc+0.3v input low voltage vil -0.3v 0.8v input leakage current ili - 10ua vin=0 to 5.5v output leakage current ilo - 10ua v out=0 to 5.5v power-down supply current icc3 - 15ua ce>vcc-0.2v standby supply current icc2 - 1.0ma ce=vih operating supply current icc1 - 25ma note 1 note: 1. measured with device selected at f=5mhz and output unloaded. 2. this parameter is periodically sampled and is not 100% teseted. 3. output low-impedance delay (tla) is measured from ce going low. 4. output high-impedance delay (thz) is measured from ce going high. ac characteristics (ta = -10 c ~ 70 c, vcc = 5.0v 10%) 23C8000-10 23c8000-12 23c8000-15 23c8000-20 parameter symbol min. max. min. max. min. max. min. max. conditions cycle time tcyc 100ns - 120ns - 150ns - 200ns - address access time taa - 100ns - 120ns - 150ns - 200ns output hold time after toh 0ns - 0ns - 0ns - 0ns - address change chip enable access time tce - 100ns - 120ns - 150ns - 200ns output enable/chip select toe - 50ns - 50ns - 50ns - 50ns access time output low z delay tlz 0ns - 0ns - 0ns - 0ns - note 3 output high z delay thz - 20ns - 20ns - 20ns - 20ns note 4
4 p/n:pm0137 rev. 4.3, jul. 03, 2003 mx23c8000 ac test conditions input pulse levels 0.4v~2.4v input rise and fall times 10ns input timing level 1.5v output timing level 0.8v and 2.0v output load see figure timing diagram propagation delay from address (ce/oe=active) valid data valid address address inputs tcyc taa data out toh note: no output loading is present in tester load board. active loading is used and under software programming control. output loading capacitance includes load board's and all stray capacitance. dout c<100pf iol (load)=2.1ma ioh (load)=-1ma propagation delay from chip enable (address valid) thz tce toe tlz oe data out ce
5 p/n:pm0137 rev. 4.3, jul. 03, 2003 mx23c8000 order information part no. access time operating current max. standby current max. package mx23c8000pc-10 100ns 25ma 15ua 32 pin dip mx23c8000mc-10 100ns 25ma 15ua 32 pin sop mx23c8000qc-10 100ns 25ma 15ua 32 pin plcc mx23c8000tc-10 100ns 25ma 15ua 32 pin tsop mx23c8000pc-12 120ns 25ma 15ua 32 pin dip mx23c8000mc-12 120ns 25ma 15ua 32 pin sop mx23c8000qc-12 120ns 25ma 15ua 32 pin plcc mx23c8000tc-12 120ns 25ma 15ua 32 pin tsop mx23c8000pc-15 150ns 25ma 15ua 32 pin dip mx23c8000mc-15 150ns 25ma 15ua 32 pin sop mx23c8000qc-15 150ns 25ma 15ua 32 pin plcc mx23c8000tc-15 150ns 25ma 15ua 32 pin tsop mx23c8000pc-20 200ns 25ma 15ua 32 pin dip mx23c8000mc-20 200ns 25ma 15ua 32 pin sop mx23c8000qc-20 200ns 25ma 15ua 32 pin plcc mx23c8000tc-20 200ns 25ma 15ua 32 pin tsop
6 p/n:pm0137 rev. 4.3, jul. 03, 2003 mx23c8000 package information
7 p/n:pm0137 rev. 4.3, jul. 03, 2003 mx23c8000
8 p/n:pm0137 rev. 4.3, jul. 03, 2003 mx23c8000
9 p/n:pm0137 rev. 4.3, jul. 03, 2003 mx23c8000
10 p/n:pm0137 rev. 4.3, jul. 03, 2003 mx23c8000 revision history revision description page date 3.4 thz:70ns max. ---> 20ns max. sep/25/1997 3.5 ac characteristics toh 10ns-->0ns p3 jan/29/1999 3.6 modify pin configutation of 32sop p1 jun/08/2000 30pin a19-->a17 ; 24pin ce/ce-->oe/oe 3.7 modify pin configuration--32tsop p1 nov/08/2000 3.8 modify package information p5~8 jul/16/2001 3.9 1. modify operating current: 40ma-->25ma p1,2 apr/25/2002 2. modify standby current: 100ua-->15ua p1,2 3. modify oe/oe-->oe; ce/ce-->ce p1,2 4.0 1. modify operating current: 40ma-->25ma p4 apr/26/2002 2. modify standby current: 100ua-->15ua p4 4.1 modify package information p5~8 nov/21/2002 4.2 1. modify "absolute maximum ratings" note p2 jun/18/2003 4.3 1. modify tace-->tce, taoe-->toe p3,4 jul/03/2003 2. modify toe:80ns(max.)-->50ns(max.) p3
mx23c8000 m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-755-834-335-79 fax:+86-755-834-380-78 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 osaka office : tel:+81-6-4807-5460 fax:+81-6-4807-5461 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

▲Up To Search▲

Price & Availability of 23C8000-10

	To Download 23C8000-10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .